Transistors can be divided into two main types: bipolar junction transistors and field-effect transistors. Both types share a common structure comprising three electrodes with a semi-conductive material disposed therebetween in a channel region. The three electrodes of a bipolar junction transistor are known as the emitter, collector and base, whereas in a field-effect transistor the three electrodes are known as the source, drain and gate. Bipolar junction transistors may be described as current-operated devices as the current between the emitter and collector is controlled by the current flowing between the base and emitter. In contrast, field-effect transistors may be described as voltage-operated devices as the current flowing between source and drain is controlled by the voltage between the gate and the source.
Transistors can also be classified as P-type and N-type according to whether they comprise semi-conductive material which conducts positive charge carriers (holes) or negative charge carriers (electrons) respectively. The semi-conductive material may be selected according to its ability to accept, conduct, and donate charge. The ability of the semi-conductive material to accept, conduct, and donate holes or electrons can be enhanced by doping the material. The material used for the source and drain electrodes can also be selected according to its ability to accept and injecting holes or electrodes. For example, a P-type transistor device can be formed by selecting a semi-conductive material which is efficient at accepting, conducting, and donating holes, and selecting a material for the source and drain electrodes which is efficient at injecting and accepting holes from the semi-conductive material. Good energy-level matching of the Fermi-level in the electrodes with the HOMO (Highest Occupied Molecular Orbital) level of the semi-conductive material can enhance hole injection and acceptance. In contrast, an N-type transistor device can be formed by selecting a semi-conductive material which is efficient at accepting, conducting, and donating electrons, and selecting a material for the source and drain electrodes which is efficient at injecting electrons into, and accepting electrons from, the semi-conductive material. Good energy-level matching of the Fermi-level in the electrodes with the LUMO (Lowest Unoccupied Molecular Orbital) level of the semi-conductive material can enhance electron injection and acceptance.
Transistors can be formed by depositing the components in thin films to form thin film transistors. When an organic material is used as the semi-conductive material in such a device, it is known as an organic thin film transistor.
Various arrangements for organic thin film transistors are known. One such device is an insulated gate field-effect transistor which comprises source and drain electrodes with a semi-conductive material disposed therebetween in a channel region, a gate electrode disposed adjacent the semi-conductive material and a layer of insulating material disposed between the gate electrode and the semi-conductive material in the channel region.
An example of such an organic thin film transistor is shown in FIG. 1. The illustrated structure may be deposited on a substrate 1 and comprises source and drain electrodes 2, 4 which are spaced apart with a channel region 6 located therebetween. An organic semiconductor (OSC) 8 is deposited in the channel region 6 and may extend over at least a portion of the source and drain electrodes 2, 4. An insulating layer 10 of dielectric material is deposited over the organic semi-conductor 8 and may extend over at least a portion of the source and drain electrodes 2, 4. Finally, a gate electrode 12 is deposited over the insulating layer 10. The gate electrode 12 is located over the channel region 6 and may extend over at least a portion of the source and drain electrodes 2, 4.
The structure described above is known as a top-gate organic thin film transistor as the gate is located on a top side of the device. Alternatively, it is also known to provide the gate on a bottom side of the device to form a so-called bottom-gate organic thin film transistor.
An example of such a bottom-gate organic thin film transistor is shown in FIG. 2. In order to more clearly show the relationship between the structures illustrated in FIGS. 1 and 2, like reference numerals have been used for corresponding parts. The bottom-gate structure illustrated in FIG. 2 comprises a gate electrode 12 deposited on a substrate 1 with an insulating layer 10 of dielectric material deposited thereover. An organic semiconductor (OSC) layer 8 is deposited over the insulating layer 10 of dielectric material. Source and drain electrodes 2, 4 are deposited over the OSC layer 8. The source and drain electrodes 2, 4 are spaced apart with a channel region 6 located therebetween over the gate electrode.
It is also known in the art to provide a thin self-assembled dipole layer on the source and drain electrodes to improve energy level matching. While not being bound by theory, a thin self-assembled dipole layer may provide a field which shifts the energy levels of the OSC near the source/drain electrodes to improve energy level matching between the OSC and the material of the source/drain. This has the effect of reducing the contact resistance at the source and drain electrodes and hence improves the performance of the TFT.
Energy level matching is required to reduce the barrier for hole injection. To do this, the work function of the source and drain materials (contacts) has to be increased, particularly in cases where the metal's work function is too low. This can be done in several ways, two of which are described following.
One way is use materials that form self-assembled mono-layers, that is molecules covalently linked to the metal surface that comprise a permanent dipole moment, such as substituted phenyls, thiols or organosilanes.
Another is to use molecules which are strong electron acceptors: where the LUMO level is below the Fermi energy level of the source and drain materials. In this case, when the material is absorbed onto the metal a spontaneous charge transfer from the metal into the LUMO of the acceptor molecule occurs, such that a layer of negatively charged acceptor molecules is formed on the surface of the metal. An example material is fluorine substituted tetracyanoquinodimethane (F4-TCNQ), which is disclosed in the Applicant's earlier application GB-A-0712269.0. US 2005/133782 and J. Am. Chem. Soc., 2006, 128, 16418-16419 also disclose the use of benzo-nitrile or substituted benzo-nitriles such as TCNQ.
Possible surface modifications of the source and drain contacts in order to provide better energy level matching include oxygen plasma treatments, UV-ozone treatments and the formation of self-assembled monolayers comprising molecules with strong permanent dipole moments, as discussed.
FIG. 3 shows a known bottom-gate organic thin film transistor wherein the source and drain electrodes have disposed thereon a thin layer of a doping material. The structure is similar to the prior art arrangement shown in FIG. 2 and for clarity like reference numerals have been used for like parts. The key difference in the arrangement shown in FIG. 3 is that a thin layer of a doping material 14, for example FTCNQ, or F4TCNQ, is inserted at the interface between the source and drain electrodes 2, 4 and the organic semiconductor 8.
FIG. 4 shows a known top-gate organic thin film transistor wherein the source and drain electrodes have disposed thereon a thin layer of a doping material. The structure is similar to the prior art arrangement shown in FIG. 1 and for clarity like reference numerals have been used for like parts. Again, the key difference in the arrangement shown in FIG. 4 is that the source and drain electrodes 2, 4 have disposed thereon a thin layer of a doping material 14, for example FTCNQ, or F4TCNQ.
The known bottom-gate implementation illustrated in FIG. 3 is usually formed using the method illustrated in FIG. 5 in which schematic cross sections are shown.                1. Gate deposition and patterning 12 (e.g. patterning of an ITO (Indium Tin Oxide) coated substrate).        2. Dielectric deposition and patterning 10 (e.g. cross-linkable, photopatternable dielectrics).        3. Deposition of the OSC 8 (e.g. by ink jet printing of a solution processable polymer).        4. Deposition of dopant layer 16 (eg by shadow masking). The dopant molecules interact with the OSC 8 where they are in contact. For an acceptor dopant with a deep LUMO, electrons are transferred from the OSC to the dopant, rendering a localised region of the OSC conducting. This improves injection and extraction of charges at the source and drain contacts.        5. Source-drain material deposition and patterning 2, 4 (e.g. shadow masking).        
This technique is also compatible with top-gate devices. In this case, the source-drain layer is deposited and patterned first (step 5 above). However, with reference to step 4 above, top-gate devices can be treated in many different ways in order to provide better energy-level matching between the source and drain contacts and the OSC, as discussed previously. For example, F4-TCNQ could be applied by spin coating as a self-assembled dipole layer, or it can be evaporated on, or it can be thickly applied using a surface treatment. In these latter two methods, the F4-TCNQ acts as a dopant layer.
Where the source-drain metal needs to be exposed (e.g. for electrical connection to a subsequent conducting layer) any thick dopant layer may need to be removed (e.g. by direct photo-patterning of a photo-reactive attachment group, laser ablation, etc) or prior surface patterning may be required to define where the dopant layer is required. Alternatively, if the F4-TCNQ layer is applied as a thin self-assembled mono-layer and is conducting enough, the F4-TCNQ can be left in situ without impeding conducting via formation.
As explained, because the source and drain contacts are deposited before the OSC in top gate devices, a lot can be done to tailor the work function of the source and drain, using the various methods described. As the semiconductor layer is deposited after the fabrication of the source and drain contacts, this allows the modification of the surface of the source and drain contacts prior to the deposition of the semiconducting layer, with the aim to increase the work function of the contacts and thereby to reduce the contact resistance within the TFT devices.
However, in contrast, the fabrication of top contact—bottom gate organic TFTs requires the deposition of metallic source and drain contacts on the top of a pre-formed semiconducting layer.
It is crucial in this case to avoid any contamination of the semiconducting layer, as the presence of redox-active and/or ionic contaminants may increase the TFT OFF current and/or will results in the occurrence of hysteresis effects. Therefore, it has been found that processes that involve chemical reactions such as electroless plating or the thermal/photochemical decomposition of metal precursors are not suitable for fabricating the source and drain contacts on top of an organic semiconducting layer. The same limitations apply to lift-off processes that involve solutions of photo-resists, resist developers and removers. In fact, most of the prior art techniques for the deposition of source and drain electrodes were developed for use with inorganic semiconductors such as silicon (and derivatives thereof) and are extremely damaging when used with organic semiconductor materials.
One technique for a contamination-less deposition of metal patterns uses thermal evaporation through the known technique of “shadow masking”. However, the resolution in such shadow mask processes is limited and it is very difficult to control—and improve—the chemical and electronic properties at the interfaces between the evaporated metal contacts and the semiconducting layer.
It has been found that using conventional techniques for applying the source and drain contacts to a bottom gate device leaves little opportunity for doping the bottom of the source and drain contacts adequately or for suitably modifying the profile of the dopant at the source/drain/dopant/OSC interface.
It is an aim of certain embodiments of the present invention to provide an improved method of depositing metallic source and drain contacts on top of an organic semiconducting layer. It is a further aim to provide an improved method of depositing metallic source and drain contacts on top of an organic semiconducting layer whilst ensuring that the resulting interfaces between the metallic contacts and the semiconducting layer are suitably doped and thereby display a low contact resistance. It is a further aim to provide an improved organic thin film transistor.